The present invention relates to the field of power supplies and, more particularly, to DC-DC converters, isolated converters or switching regulators wherein controlling the primary and secondary output voltages is desired.
Switching regulators, including ripple regulators, are commonly used because of their characteristic of high efficiency and high power density (i.e., power-to-volume ratio) resulting from smaller magnetic, capacitive, and heat sink components. In current mode control, switching regulators indirectly regulate an average DC output voltage by selectively storing energy by switching energy on and off in an inductor. By comparing the output voltage to a reference voltage, the inductor current is controlled to provide the desired output voltage. The above refers to current mode control; other modes of control include voltage mode control. Ripple regulators use other methods.
Synchronous buck power stages are a specific type of switching regulator that use two power switches such as power MOSFET transistors. A high-side switch selectively couples the inductor to a positive power supply while a low-side switch selectively couples the inductor to ground. A pulse width modulation (PWM) control circuit is used to control the high-side and low-side switches. Synchronous buck regulators provide high efficiency when low on-resistance power MOSFET devices are used.
With increased demand for low voltage power, the synchronous rectifier (SR) is now an important circuit element in the DC-DC converter mainstream. One such use of the synchronous rectifier is the low-side switch in buck power stages.
The added emphasis on synchronous rectification is also posing design problems for the DC-DC converter designer. The synchronous rectifier is generally more difficult to use than a traditional diode rectifier. Typical SR design considerations include gate timing control, gate driver, and reverse conduction. However, because traditional diode rectifiers can account for over 50% of the total power loss in modern 3.3V output converters (significantly higher for lower output converters), more and more converters are being forced to use the more efficient SR, despite its complexity. However, significant power losses are still resulting from the delay necessary for switching on states between the high side and low side to prevent the simultaneous conduction of the high-side and the low-side switches. To maximize power efficiency, it is desirable to minimize the delay times to an optimal level, while preventing simultaneous cross-conduction of the high-side and low-side switches.
A pulse width modulating control circuit is used to control the high-side and low-side switches. However, it has been found that controlling the timing of the high-side switch and the low-side switch has resulted in inefficient operation due to body diode conduction in the low-side switch.
As before, PWM isn""t the only technique. Ripple regulators and pulse frequency modulation (PFM) are other techniques which are popular. Inside PWM techniques are three methods which include voltage mode, peak current mode and average current mode.
The present invention is applicable for a buck circuit, a boost circuit, and a buck-boost circuit as well as the isolated topologies derived from buck, boost and buck-boost in order to accurately control the time that the high-side driver is on with respect to the low-side driver. More particularly, the present invention senses the voltage of the terminal between the high-side switch and the low-side switch to provide an indication of how long to delay the pulse to activate the high-side switch or the low-side switch.
The circuit of the present invention is predictive and learning by the operation of the circuit itself. The present invention sets time delays to a minimum value to avoid shoot-through current. By use of a learning circuit, the present invention responds to component and parameter changes, keeping the minimum delay time. Since the circuit of the present invention is predictive, and most time delays are temperature dependent, temperature variation is easily compensated for. By minimizing the non-overlay times, where the body diode of a SR conducts, power losses are minimized.
The present invention controls the delay times by monitoring the voltage across the SR drain-to-source to detect if the body diode is conducting. The circuit then can adjust the delay to be longer or shorter to minimize the conduction of the body diode.